Need document for IO PAD based design

[vijayank88]

Description

Referring the source rtl from here. IO pad tcl script from here. coyote_tc netlist from here.

But if I run ORFS based flow config.mk the generated netlist different from OpenROAD skywater130_coyot_tc/coyote_tc.v test case netlist.

OpenROAD test case netlist:

sky130_fd_io__top_gpiov2 \u_clk.u_in  (
    .AMUXBUS_A(AMUXBUS_A ),
    .AMUXBUS_B(AMUXBUS_B ),
    .ANALOG_EN(_139307_),
    .ANALOG_POL(_139307_),
    .ANALOG_SEL(_139307_),
    .DM({ _139307_, _139307_, _139306_ }),
    .ENABLE_H(_139306_),
    .ENABLE_INP_H(\u_clk.tie_lo_esd ),
    .ENABLE_VDDA_H(_139306_),
    .ENABLE_VDDIO(_139306_),
    .ENABLE_VSWITCH_H(_139307_),
    .HLD_H_N(_139306_),
    .HLD_OVR(_139307_),
    .IB_MODE_SEL(_139307_),
    .IN(clk),
    .INP_DIS(_139307_),
    .IN_H(),
    .OE_N(_139307_),
    .OUT(_139307_),
    .PAD(clk_i),
    .PAD_A_ESD_0_H(),
    .PAD_A_ESD_1_H(),
    .PAD_A_NOESD_H(),
    .SLOW(_139307_),
    .TIE_HI_ESD(\u_clk.tie_hi_esd ),
    .TIE_LO_ESD(\u_clk.tie_lo_esd ),
    .VTRIP_SEL(_139307_)
  );

ORFS setup generated netlist:

sky130_ef_io__gpiov2_pad_wrapped \u_clk.u_in  (
    .AMUXBUS_A(\u_clk.AMUXBUS_A ),
    .AMUXBUS_B(\u_clk.AMUXBUS_B ),
    .ANALOG_EN(_153328_),
    .ANALOG_POL(_153328_),
    .ANALOG_SEL(_153328_),
    .DM({ _153328_, _153328_, _153327_ }),
    .ENABLE_H(_153327_),
    .ENABLE_INP_H(\u_clk.tie_lo_esd ),
    .ENABLE_VDDA_H(_153327_),
    .ENABLE_VDDIO(_153327_),
    .ENABLE_VSWITCH_H(_153328_),
    .HLD_H_N(_153327_),
    .HLD_OVR(_153328_),
    .IB_MODE_SEL(_153328_),
    .IN(\u_clk.y ),
    .INP_DIS(_153328_),
    .OE_N(_153328_),
    .OUT(_153328_),
    .PAD(clk_i),
    .SLOW(_153328_),
    .TIE_HI_ESD(\u_clk.tie_hi_esd ),
    .TIE_LO_ESD(\u_clk.tie_lo_esd ),
    .VTRIP_SEL(_153328_)
  );
  sky130_sram_1rw1r_64x256_8 \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0  (
    .addr0({ \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[7] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[6] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[5] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[4] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[3] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[2] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[1] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.W0A[0]  }),
    .addr1({ \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[7] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[6] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[5] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[4] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[3] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[2] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[1] , \u_coyote.r2f.rocket.RocketTile.dcache.data.T112.R1A[0]  }),
    .clk0(\u_clk.y ),
    .clk1(\u_clk.y ),
    .csb0(\u_coyote.r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.CENB ),

From the flow setup, I understand like ios.v template mapping RTL with PAD connection. Is the default template to use for IO PAD connection?

How to map the IO name with place_pad script? Based on netlist or source rtl?

If IO pads defined in sub level hierarchy, is possible to place? If yes provide syntax format to use.

It is helpful, if add reference document on IO pad based design. i.e., how to create source RTL if user wants to create IO pad based design, how to use through config.mk and how to create place_pad script for IO pad placement during floorplan, PDN for IO pad based design.

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Additional Context

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[dralabeing]

@vvbandeira @luarss Let's add this to our doc completion list