OpenLane icon indicating copy to clipboard operation
OpenLane copied to clipboard

Clock Network Delay is 0.0 in timing reports after CTS

Open Jaswanth-Pappula opened this issue 1 year ago • 2 comments

Clock Network Delay is showing as 0.00 in timing reports of Max and Min after CTS step even though CTS routing is completed.

You can find it in the image attached below.

Picture1

Can someone help me in resolving this issue.

Jaswanth-Pappula avatar Apr 26 '24 02:04 Jaswanth-Pappula

Most likely you need set_propagated_clock [all_clocks]

maliberty avatar Apr 26 '24 03:04 maliberty

Most likely you need set_propagated_clock [all_clocks]

set_propagated_clock [get_clocks {Clk}] is generated in the cts.sdc file inside results section of the design but nor replicated in the min, max or nominal timing reports and it is just showing ideal.

so, is there any other way to do it instead of using set_propagated_clock [all_clocks]. image

Jaswanth-Pappula avatar Apr 27 '24 12:04 Jaswanth-Pappula

Should be fixed by now.

donn avatar Aug 05 '24 12:08 donn

Should be fixed by now.

Yes, the problem is fixed. Thanks for the reply

Jaswanth-Pappula avatar Aug 05 '24 14:08 Jaswanth-Pappula