Mismtach between ports for `sky130_fd_sc_hd__tapvpwrvgnd` in physical views and verilog model

[kareefardi]

Description

Expected Behavior

Environment report

<will add later>

Reproduction material

Relevant log output

<will add later>

[d-mitch-bailey]

@kareefardi I haven't been seeing a problem in device level lvs with this cell abstracted. Maybe there's a problem with lef lvs?

[kareefardi]

@d-mitch-bailey this mistmatch wouldn't really cause any errors. It is just flooding Verilator with warnings about disconnected pins.

[d-mitch-bailey]

Is there an option in verilator to ignore certain cells? Don't fill cells give the same error.

[kareefardi]

This was mainly caused by including gate level netlists through VERILOG_FILES_BLACKBOX. Since we blackbox these files now, such warnings are not generated. However the main issues still remains.

Is there an option in verilator to ignore certain cells? Don't fill cells give the same error.

Unfortunately, I don't know a way to really do that in Verilator.