Special cells should be marked as dont use by synthesis

[mguthaus]

Description

clkbuf cells are used as standard cells. These should be excluded during synthesis and resizing since they are balanced and probably not "efficient" in terms of area. Example where a short path is using a clkbuf:

Expected Behavior

I would expect clkbuf cells to be excluded from everything but CTS.

Environment report

Kernel: Linux v6.0.12-76060012-generic
Distribution: pop 20.04
Python: v3.9.12 (OK)
Container Engine: docker v23.0.5 (OK)
OpenLane Git Version: ed194238ac359aca044c54fa8cbbbd12280e1a8c
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: FAILED
/home/mrg/courses/OpenLane/pdks/sky130A not found.
Traceback (most recent call last):
  File "/home/mrg/courses/OpenLane/dependencies/verify_versions.py", line 76, in verify_versions
    raise Exception(f"{pdk_dir} not found.")
Exception: /home/mrg/courses/OpenLane/pdks/sky130A not found.

Failed to verify sky130A.
---
Git Log (Last 3 Commits)

ed194238 2023-03-29T15:14:23+02:00 Move Timing Checks After Report Generation (#1706) - Mohamed Gaber -  (HEAD -> master, tag: 2023.03.30, origin/master, origin/HEAD)
c2944188 2023-03-29T14:34:48+02:00 Revert "#1703" (#1705) - Mohamed Gaber -  ()
54d5b5a3 2023-03-29T14:01:00+02:00 Fix regression in #1685 (#1703) - Mohamed Gaber -  ()
---
Git Remotes

origin	https://github.com/The-OpenROAD-Project/OpenLane (fetch)
origin	https://github.com/The-OpenROAD-Project/OpenLane (push)

Reproduction material

I synthesized picorv32a with a clock period of 6ns.

Relevant log output

See above timing path.

[kareefardi]

Seems like a similar issue to the one raised here https://github.com/The-OpenROAD-Project/OpenLane/issues/1035

[Wren6991]

These should be excluded during synthesis and resizing since they are balanced and probably not "efficient" in terms of area

Using clock buffers on datapath isn't inherently bad. On commercial libraries with a bigger catalog of balanced cells, like ckand/ckxor, I occasionally see these used for datapath and assume the tools made the right choice. They may land between the normal integer buffer sizes in terms of delay and area.

Excluding for synthesis makes sense as it's not physically aware, but could the resizer pick the lowest area for the required timing change?