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Provide a Spice model of final circuit that includes parasitics

Open growly opened this issue 3 years ago • 5 comments

Description

It seems useful to provide a Spice model that includes extracted parasitics at the end of the flow. Proprietary tools readily make this available, and it makes sense to provide the parasitics in a format readily available for the user's simulations.

Proposal

I don't know if existing tools in the flow can do this, but BigSpicy can. It can merge Verilog, Spice and SPEF netlists. It can also do things like

  • extract capacitively-coupled networks
  • extract paths between given input/output nodes
  • flatten the design to the transistor level (for analog designers)

It can easily be run as a (possibly optional) step in the flow to dump the merged Spice view for the user.

Ideally we wouldn't have to export to SPEF and Spice and then re-merge them, but absent another option this does work.

growly avatar Dec 12 '22 09:12 growly

Absolutely chuffed that its name is "BigSpicy." We can integrate it, sure, that does sound incredibly useful.

donn avatar Dec 12 '22 14:12 donn

Most blocks will be far too large to spice. You might find write_path_spice in opensta more useful.

maliberty avatar Dec 12 '22 15:12 maliberty

I don't agree. Without making any assumptions about what "most" blocks look like, consider that:

  • Simulators like Xyce are designed to make full-chip simulation feasible
  • Blocks which do not benefit from large scale Spice simulation do not need to use this feature
  • Blocks which do benefit will gain greatly from this feature
  • I have used BigSpicy and Xyce to analyse hardened macros with success (I could simulate one cycle of a floating point multiplier in a couple of minutes on my workstation, and one cycle is all I needed)
  • Last I checked, write_path_spice did not include parasitics

growly avatar Dec 12 '22 20:12 growly

If this is useful then great.

write_path_spice does include parastics, otherwise it wouldn't useful. That's not new.

maliberty avatar Dec 13 '22 13:12 maliberty

My mistake, I misremembered why I couldn’t use write_path_spice. I needed a way to find all nets coupled to a path by some capacitance threshold and it couldn’t give me that, if I recall correctly this time.

It might be better to enable OpenSTA to dump the whole netlist with parasitics? But that would be more work

growly avatar Dec 13 '22 13:12 growly