Add opensta command check_setup in final report and also after synthesis to check SDC completeness

[tspyrou]

Prompt

A clear and concise description of what shortcoming you feel OpenLane has.

Proposal

A clear and concise description of what you want to happen.

[antonblanchard]

@tspyrou I tried this out and noticed a few places where check_setup gives false positives:

• input ports that are unused. There's no timing issue here, but perhaps the warning is useful. It might be nice to report it as unconnected.
• output ports that are tied high or low, or FFs that have their input tied low or high. I'm not sure how OpenROAD could resolve this (perhaps if we passed the tie cell name).