Format not well set for case operator

[lukipedio]

See example below

[qarlosalberto]

It is complex to modify the formatter. We will improve it in the future

[qarlosalberto]

@lukipedio could you share the code (no image)? So I can test it.

[lukipedio]

Sure! Sorry I missed the notification. src.zip

What I complain about is:

• The state machine format: some case have a different indentation/formatting
• port and signal name are uppercase (itis not my default choice): I think this could be configured by vsg

Thanks for checking.

Using Tesroshdl 0.4

[qarlosalberto]

In the new version (v0.0.5) port and signal name aren't uppercase