VHDL: some comments are not integrated to module documentation

[lepommosaure]

Hi everyone,

First of all: Thank you for your dedicated work bringing the world this great extension!

I am running into the following issue when using "Module documentation preview" with VHDL files: some comments are ignored I am using Windows 10

Typically, the following comments will not show up in the module documentation at all:

• The last signal declaration
• The first process description in the architecture

Also, the processes in for-generate are not detected in the doc. preview

I am joining an example source file and a screenshot of the output

test_file.zip

[qarlosalberto]

Thanks @lepommosaure we will fix it :)

[davemaster]

thank You

El jue, 11 mar 2021 a las 3:58, Carlos Alberto Ruiz Naranjo (< @.***>) escribió:

Thanks @lepommosaure https://github.com/lepommosaure we will fix it :)

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[holzi-x]

In addition to the fix I can state, that for example process descriptions are all included if the first line after the 'begin' keyword of an architecture is not a process definition but let's say a signal assignement. Obviously the parser needs one line not containing a known keyword to work correctly

[qarlosalberto]

fixed on v5.0.0