VHDL component template not translating well Verilog reg types

[somhi]

Describe the bug When generating template from Verilog module to VHDL component, reg verilog types are not well translated

To Reproduce generate template VHDL component from https://github.com/TheSonders/USBKeyboard/blob/main/ULPI_PS2_PUBLIC.v

Code output reg PS2data, from Verilog is translated into PS2data : out reg; should be translated I think into PS2data : out std_logic (I'm not expert in VHDL)

Please complete the following information:

• OS: Ubuntu 20.04
• TerosHDL 2.0.6
• VSCode version 1.62.3

Screenshots