vscode-terosHDL Go to definition for module

I find that the plug has a feature: Go to definition for variable，is there a feature that Go to definition for module?

Apr 23 '21 01:04 qgzln

In the next release we will support it. But only for VHDL.

El vie., 23 abr. 2021 3:49, qgzln @.***> escribió:

I find that the plug has a feature:Go to define for variable，is there a feature that go to define for module?

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Apr 23 '21 08:04 qarlosalberto

In the next release we will support it. But only for VHDL. El vie., 23 abr. 2021 3:49, qgzln @.***> escribió: … I find that the plug has a feature:Go to define for variable，is there a feature that go to define for module? — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#132>, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABNN4R24NHNRETNKQ4YALQ3TKDGYZANCNFSM43NWGZJA .

I use Verilog，when will it support for Verilog

Apr 23 '21 11:04 qgzln

Maybe in the next months, but no in the next release.

Jun 01 '21 12:06 qarlosalberto