vscode-terosHDL
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Wavedrom rendering not available in processes
Wavedrom waveform are not rendered when added in process descriptions (for (System)Verilog). Instead, the wavedrom code is directly printed as normal text.
//! Shadow register update
//! *format*
//!
//! {signal:[
//! {name:'clock',wave:'HLHLHLHL'},
//! {name:'valid',wave:'1.0.....'}]}
//!
always_ff @(posedge i_clk or negedge i_rst_n)
begin : p_shadow_transfer
if(~i_rst_n)
begin
shadow_output <= 0;
end
else
begin
shadow_output <= i_d;
end
end

Currently it's only supported in the entity description. We could add it in the process description.