PeakRDL-uvm
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[v3.0] hdl_path property does not work with regard to addrmap and regfile components
Hi, I write SystemRDL like this:
addrmap root_map {
hdl_path = "root_map";
test_map_1 test_map_1_inst;
test_map_2 test_map_2_inst;
test_map_3 test_map_3_inst;
test_map_3_inst -> hdl_path = "test_map_3_inst";
};
where test_map_3_inst
is a addrmap component instance. The question is, as you can see, I dynamically assign a hdl_path property to test_map_3_inst
, but in generated UVM RAL model, the hdl_path is not generated:
It seems like only register components with hdl_path properties results in a add_hdl_path_slice() function call, like this:
addrmap test_map_3 {
hj_genrtl = false;
shared_tem shared_3[5];
shared_3 -> hdl_path = "shared_3";
shared_3 -> name = "SHARED_IN_TEST_MAP_3";
shared_3.FIELD_1 -> sw = r;
shared_3.FIELD_1 -> onread = rclr;
};
where shared_3
is a reg
component instance, and generated UVM RAL:
virtual function void build();
this.default_map = create_map("reg_map", 0, 4, UVM_NO_ENDIAN);
foreach(this.shared_3[i0]) begin
this.shared_3[i0] = new($sformatf("shared_3[%0d]", i0));
this.shared_3[i0].configure(this);
// hdl_path add here
shared_3[i0].add_hdl_path_slice("shared_3", -1, -1);
this.shared_3[i0].build();
this.default_map.add_reg(this.shared_3[i0], 'h0 + i0*'h4);
end
endfunction : build
Being not familiar with UVM, in my opinion, ultimately all hdl_path
in different hierarchies will be concatenated for RTL design verification. Is there some special consideration about the hdl_path
property assigned in different components?
I'm not an expert in RDL, but the RDL spec on page 80 has an example of overriding this, and it uses parameters. Maybe try that?
Just wanted to post here that I did not forget about this issue.
I'm planning a significant refactor of the UVM generator (see issues tagged in v3.0
milestone), and plan to address this then.