verilog_grapher
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Graph your gate-level verilog code as a directed graph!
verilog_grapher
Visualize your gate-level verilog code as a directed graph. networkx library was used to draw the graphs
Running
Run the following command:
python3 main.py <path-to-verilog-file>
Graphical Representation of a Full Adder
Improvements!
- Improve the parser
- Improve the positioning of nodes in graph