Introduction

[PythonLinks]

First thank you for creating this repository.

I plan on using this to generate many core Forth processors. You can read more about my plans here. https://forth.pythonlinks.info

Probably initially as an audio synthesizer. There are a bunch of us interested in audio synthesis on the pico-ice discord server.

You may have seen my SVFIG talk on "A review of Forth Soft Core Processors"

https://www.youtube.com/watch?v=qgmrZoJyHUw

More recently I did the same talk at the Stockholm FPGA conference. Here are the updated slides. https://pythonlinks.info/presentations/StockholmConference.pdf

It turns out that the Mecrisp Forth interpreter is 200 times smaller than the Python interpreter. Wow.

I recently bought the Pico-Ice and the Upduino FPGA boards. I released an echo server for the Pico-Ice. https://forth.pythonlinks.info/pico-ice-echo-server

Then I got Mecrisp Forth running on the Pico-Ice. But it took up way too many resources. ICESTORM_LC: 2604/ 5280 49%

Hard to buld a many core, when half the luts are already used.

But there is a more important reason to switch to this software stack. If you look at the Mecrisp source code, it support some 12 boards, and 28 different options in the verilog files. Really hard to mange that complexity in pure Verilog. Much better to do it in a high level language.

I took a look at MyHDL, did not like it. They generate the code, but throw out hierarchy information at simulation time, making debugging harder. Amaranth did not resonate with me either. I took one look at SpinalHDL, and everything looks very reasonable, even fantastic. I can refer to something in another branch of the hierarchy without having to manage wires up and down the stack. Awesome.

Not only I think so. The VexRiscV which won the first prize at the RISC-V Summit softCore contest, was also written in SpinalHDL

https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html

Also I think it is much better to start with a tiny core, and only add in the stuff that I need.

As for issues, I wish that there were a newer release of this software, and I wish that more Electrical Engineers were aware of the advantages of high level languages, and were using this software, instead of sticking to Verilog and VHDL. Oh well.

Wish me luck.