xschem
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StefanSchippers
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Dear all, I recently installed Xschem version 3.4.5. I have started with an example with a simple mosfet and two voltage supplies to check the operation point. As soon as...
Hello! I have a question - is it possible to define custom type of the pin, for example, electrical type, magnetic, thermal, signal, etc, and when wire is connected to...
This is probably a bad idea but curious for your thoughts. Feel free to close without comment as always. Problem: Screenshots in bug reports and tutorials can be hard to...
As we have enabled [Schematic driven layout](https://gdsfactory.github.io/gplugins/notebooks/20_schematic_driven_layout.html) in [gdsfactory](https://gdsfactory.github.io/gdsfactory/) it would be great to have an extension for xscheme, so that we can automatically create symbols from our PDK Pcells...
How could we enable [sax](https://flaport.github.io/sax/) and [scikit-rf](https://github.com/scikit-rf/scikit-rf/issues/352) for RF circuit simulations from xschem? @flaport @proppy
I'm trying to build xschem under Big Sur on my M1 Mac, following the guidance that's in the revised Mac OS build instructions that was figured out in this issue:...
Hi Stefan, I'm just wondering if there's a way to know or generate a spice report to see what the region of operations of your transistors in your respective design?...
Hello! I'm having some trouble when trying to launch xschem with SkyWater models. In my other computer, when I type "xschem &" it runs, but in the PC I'm using,...
I have successfully installed xschem, and tried to run an already given circuit in the library. I'm able to generate the netlist but I'm not able to simulate. I'm attaching...
will require some significant work.
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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.