StefanSchippers

Hi, George, net / pin types are already used for VHDL. a sig_type attribute is attached to a net / pin to define the type of the signal, since VHDL...

You can send a cut-down example of your design containing two or more signal domains. Create a new empty directory (example/), place the schematics and symbols used into this directory....

I have created the following script: ``` proc hilight {} { set color(magnetic) 0 ;# red set color(electrical) 1 ;# yellow set color(mech_trans) 2 ;# white foreach item [xschem list_nets]...

It is not clear to me how an electrical ground (like 0) relates to a "magnetic" ground. If they are different things they should have different labels. In your ground...

Ok, understood. So you can modify the script to not consider the '0' node (it can be connected to any domain, so highlighting it does not make sense).

For in, out, inout pins of a subcircuit schematic, add the **class=...** attribute, as well as to the corresponding pins in the symbol. I prefer the user takes the task...

the 0-voltage sources (ammeter) are the best way to create net aliases. One caveat: the 0 node is by definition global, so it has the same meaning in every subcircuit...

Of course you can. Still curious why a 0V vsource for a net aliasing makes simulation fail.

Can you try to alias a gnd node by using a 0.000001 (or similar "low enough" value) Ohm resistor?

you can posprocess the netlist, transforming all: Vxxxx node1 node2 0 to RVxxxx node1 node2 0.000001 and see if simulation works. No need to tamper the schematic of course, unless...