[Bug] CSR writes to cycle/instret do not raise illegal-instruction

[canxin121]

Reproduction

Minimal program (user_code only):

li x17, 1
csrrs x18, cycle, x17
csrrs x19, instret, x17

Issue

• Expected: cycle and instret are read-only CSRs; csrrs with rs1!=x0 should raise illegal-instruction and must not write back to GPRs.
• Actual: Spike raises illegal-instruction on both instructions; VexRiscv does not trap and retires normally, updating x18/x19 with the counter values.

[Dolu1990]

Hi,

Yes right. That would need to be fixed.