How to interface with a VHDL module with Axi4

[cofleury]

Hi, I have a module written in VHDL which has an Axi4 interface and I would like to interface it with the Axi4 class of the SpinalHDL so I can use it inside the Vex. My question is: what are the steps I need to follow to do this ? As of now I created a SpinalHDL wrapper around the VHDL module. Then I created a class which instantiates this module and now I am trying to connect the VHDL ports to the corresponding class ports:

class CustomModuleAxi() {

    val module = CustomModule() //Default param
    object axi_config = Axi4Config(
        dataWidth = 32,
        useId = False,
        useQos = False,
        useRegion = False,
        useLock = False,
        useCache = False,
        useBurst = False,
        useSize = False,
        useLen = False,
        useProt = False,
        useUser = False,
        useStrb = False,
        useResp = False
    )

    val io = Bundle(
        axi_slave = slave(Axi4Shared(axi_config))
    )

    io.axi_slave.writeRsp.ready := module.io.S_Tready_o
    io.axi_slave.writeRsp.valid := module.io.M_Tvalid_o
    io.axi_slave.writeRsp.last := module.io.M_Tlast_o
}

How can I say for instance that the writeData ports will be connected to the register-file ?