RFE: limit cache tag width

[hpax]

It is relatively common in embedded operations that only a relatively small subset of the memory space is cacheable, or even executable. In my experimentation (using a Cyclone IV E), I have found that the width of the cache address tags appear to be a strong Fmax limiter, at least with RVC enabled.

As such, it would be ideal to have the option for the [ID]busCachedPlugins to be able to specify the cache tag address width separately from the memory bus address. This of course requires either that the memory space is configured with a narrow enough mask for the cacheable region, or that aliasing across the cacheable region is acceptable. However, if the memory is narrower than the cacheable region then such aliasing will happen anyway, and one could even argue that aliasing already in the cache is preferable in that case, as it avoids the possibility of inconsistent entries in the cache that might escape invalidation.

This is different, however, from the width of the output memory bus, as that includes noncacheable regions.