Zephyr - new FPU context switch not working in VexRiscV-smp CPU

[pottendo]

hi, upfront, I hope this isn't too off-topic for this project. Let me know and in case direct me to the correct place, e.g. the LiteX repo... thanx.

Summary: Zephyr 3.3-RC1 introduced a new (optimized) handling of FPU register saving in mutli-threaded applications (context switch). My Litex-project uses a VexRiscV-smp SoftCPU core. I got basic Zephyr running on this project by just providing a matching devicetree - find the links in the issue report.

Find all details to this issue in the Zephyr repository. The Zephyr author @npitre suggests:

Alright. Since you do have access to the CPU implementation source code,
I think it would be far better for you to figure out how to support the
MSTATUS_FS bits in your project.

So as I haven't managed to get it going on my own, I ask you experts here! As a fallback I could revert to 3.2.99 version of Zephyr's FPU code; but I'd like to understand if the problem is either in my Zephyr port, my RiscV Litex project or even something which would be required to be fixed/added in the VexRiscV-smp CPU itself. If it's the very last reason, other's may encounter this problem as well.

Thanks for any feedback, pottendo