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equivalent constructs at elaboration time/hardware/sim

Open numero-744 opened this issue 1 year ago • 5 comments

numero-744 avatar Nov 16 '22 16:11 numero-744

@Readon

What do you think of this?

https://sublime-and-sphinx-guide.readthedocs.io/en/latest/code_blocks.html#code-examples-in-multiple-languages

Maybe do the same thing for VHDL vs SystemVerilog vs SpinalHDL?

numero-744 avatar Nov 16 '22 16:11 numero-744

that would be great if there are SpinalHDL/Verilog/SystemVerilog/VHDL,user can easily compare and study by that.

However, it's necessary to make that happen.

---Original--- From: @.> Date: Thu, Nov 17, 2022 00:29 AM To: @.>; Cc: @.@.>; Subject: Re: [SpinalHDL/SpinalDoc-RTD] equivalent constructs at elaborationtime/hardware/sim (Issue #145)

@Readon

What do you think of this?

https://sublime-and-sphinx-guide.readthedocs.io/en/latest/code_blocks.html#code-examples-in-multiple-languages

Maybe do the same thing for VHDL vs SystemVerilog vs SpinalHDL?

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Readon avatar Nov 16 '22 17:11 Readon

However, it's necessary to make that happen.

@Readon I'm focusing on RTD for the next 2 weeks, we'll see what it gives ^^

I wanted a big rework of RTD, I have started this morning. I'm waiting for other PRs to be merged (automated code checks and pdf generation in GH workflow) before I publish a PR.

After this I'll address RTD issues like this one.

numero-744 avatar Nov 16 '22 17:11 numero-744

Can be fancy :D

Dolu1990 avatar Nov 16 '22 19:11 Dolu1990

Ooops https://github.com/svx/sphinxcontrib-osexample/issues/8

numero-744 avatar Nov 17 '22 22:11 numero-744