Kronos LUT usage

[MrJake222]

Hi,

May I ask how to synthesize such a small Kronos core as the README mentions (~2k LUT4)? I use sv2v, yosys and nextpnr. My workflows give around ~5k exceeding iCE40UP5K avaliable resources:

$ git clone https://github.com/SonalPinto/kronos.git
$ cd kronos/rtl/core
$ sv2v *.sv > kronos_all.v
$ yosys -p "synth_ice40 -top kronos_core -json kronos_all.json" kronos_all.v
...
2.49. Printing statistics.

=== kronos_core ===

   Number of wires:               3079
   Number of wire bits:          12925
   Number of public wires:        3079
   Number of public wire bits:   12925
   Number of ports:                 16
   Number of port bits:            174
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6346
     $scopeinfo                     12
     SB_CARRY                      270
     SB_DFFE                      1491
     SB_DFFER                      237
     SB_DFFESR                     141
     SB_DFFESS                       9
     SB_DFFR                        15
     SB_DFFS                         1
     SB_LUT4                      4170

$ nextpnr-ice40 --up5k --package sg48 --json kronos_all.json
...
Info:            ICESTORM_LC:    5460/   5280   103%
...

My question is whether Verilog conversion does harm, or I'm doing something wrong? Should I disable something in config somewhere? Disabling fast branching, counters and catching barely brings it down below 5k LUT.