kronos
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SonalPinto
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
Hello! Does this repo support RTL simulation like Verilator? Thanks in advance
**Describe the bug** On the Kronos RISC-V processor, instructions that operate on non-existent Control Status Registers (CSRs) are executed successfully without raising an exception(as described in issue #9 ). This...
I have found a security vulnerability where the execution time is influenced by the data operand of an 'addi' instruction. The following test bench reproduces the problem. When setting the...
Hello, I have found a security vulnerability where an addi (or slti) instruction can unexpectedly write into the mtvec CSR and therefore manipulate the trap handler execution location unexpectedly. The...
Hi there! In complement to #7 , I noticed that reading existing CSRs also causes the CPU to hang. This happens only if the destination register is distinct from `zero`....
Hi there! This PR fixes #8. Thanks! Flavien
Hi there! ### Bug description I think I found a bug not described in the issues and PRs in this repo. `minstret` seems to overcount. ### Example snippet The stored...
Hi there! I've detected a bug in Kronos, which complements #7 . ## Brief bug description Writing non-existent CSR does not raise an illegal instruction exception. The RISC-V specification says:...
Hi there! I've detected a bug in Kronos. ## Brief bug description Accessing non-existent CSR does not raise an illegal instruction, but instead hangs after a couple of instructions later....
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Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations