Siudya
More resources are used when project is rebuilt and synthesised
Would you do me a favor? I need some help. It costed 139115 luts when the file called comDescriptor.cpp was synthesised. I followed your steps to rebuild vivado project， but i failed. Thanks!
It doesn't matter. After implement and routing, it would be optimized. It would cost about 9000+ LUT.
------------------ 原始邮件 ------------------ 发件人: "jianyi324"<[email protected]>; 发送时间: 2020年7月25日(星期六) 晚上8:37 收件人: "Siudya/ORB_FPGA"<[email protected]>; 抄送: "Subscribed"<[email protected]>; 主题: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)
Would you do me a favor? I need some help. It costed 139115 luts when the file called comDescriptor.cpp was synthesised. I followed your steps to rebuild vivado project， but i failed. Thanks!
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555... I'm confused! Could you give me your email? I want to show you my picture about vivado project! Thanks!
555.... 一开口就知道是中国人了 [email protected] 你发这个吧
------------------ 原始邮件 ------------------ 发件人: "jianyi324"<[email protected]>; 发送时间: 2020年7月25日(星期六) 晚上9:30 收件人: "Siudya/ORB_FPGA"<[email protected]>; 抄送: "梁森"<[email protected]>; "Comment"<[email protected]>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)
555... I'm confused! Could you give me your email? I want to show you my picture about vivado project! Thanks!
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I encountered the same problem, old brother.
During comDescriptor synthesis, the Summary showed that the available resources FF and LUT on the chip exceeded a lot.
as the picture shows:
It doesn't matter. After implementing the cost will be optimized down to an acceptable level.
------------------ 原始邮件 ------------------ 发件人: "Albert"<[email protected]>; 发送时间: 2020年8月9日(星期天) 上午10:39 收件人: "Siudya/ORB_FPGA"<[email protected]>; 抄送: "梁森"<[email protected]>; "Comment"<[email protected]>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)
I encountered the same problem, old brother. During comDescriptor synthesis, the Summary showed that the available resources FF and LUT on the chip exceeded a lot. as the picture shows:
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According to the code, I have copied the .bit and .hwh files to the corresponding locations. Then, a problem occurred.
First, the .bit file is successfully loaded, and you can see that the overlay object has 4 IP Blocks:
axi_dma_FAST; axi_dma_Gaus; axi_dma_des_2Mem; axi_intc_0.
However, when calling IP Blocks whose type is pynq.lib.dma.DMA, an error will occur (take FAST as an example):
Have you encountered similar problems? my old brother.
Sorry but I never encounter the problem. Did you use pynq 2.4 or higher with the .bit and .hwh files provided in the repo? Maybe a rebooting can make it work :P .
------------------ 原始邮件 ------------------ 发件人: "Albert"<[email protected]>; 发送时间: 2020年8月13日(星期四) 晚上8:13 收件人: "Siudya/ORB_FPGA"<[email protected]>; 抄送: "梁森"<[email protected]>; "Comment"<[email protected]>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)
According to the code, I have copied the .bit and .hwh files to the corresponding locations. Then, a problem occurred. First, the .bit file is successfully loaded, and you can see that the overlay object has 4 IP Blocks: axi_dma_FAST; axi_dma_Gaus; axi_dma_des_2Mem; axi_intc_0.
However, when calling IP Blocks whose type is pynq.lib.dma.DMA, an error will occur (take FAST as an example):
Have you encountered similar problems? my old brother.
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old brother,Sorry to disturb you. I could not find the constraint xdc file of the vivado project in the pynq_arch folder. I really want to figure out how the pin constraints of your project are allocated.
No contraints are needed. All the pins are set via board files. (only sysclk is connected to a PL pin)