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A language-agnostic JSON-encoded instruction-by-instruction test suite for the 8088, 68000, 65816, 65[c]02 and SPC700 that includes bus activity.

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Looking at the 68000 tests, it seems that the initial state of the CPU for each test is seemingly random. I don't seem to find the generator (I guess it's...

This repo is getting a bit huge; and I will have another set to contribute soon which is going to make it even bigger. What would you think about making...

There are a lot of rare edge cases in 65816 that depend on an address being XXFF or FFFF and then adding an offset. For example, an operand might be...

enhancement

A number of people who have used the 8088 tests have struggled validating division. The main issue is the division exceptions that occur, which results in the flag register with...

Given the growing popularity of these tests, I have noticed a significant increase in questions regarding the accuracy and source of the test data. There are also known issues with...

According to [65C816 Opcodes by Bruce Clark](http://www.6502.org/tutorials/65c816opcodes.html), because these instructions / addressing modes are new (not present on 65*02), they should not page wrap: - 17.e.json: ORA [d],y - 57.e.json:...

``` { "name": "02 35 44", "initial": { "pc": 1837, "s": 197, "a": 33, "x": 239, "y": 61, "p": 108, "ram": [ [1837, 2], [1838, 53], [1839, 68]]}, "final": {...

Hello -- While testing against my in development 65C02 core, I noticed that the STZ opcode tests have no way of knowing if the zero was actually written if you...

bug

I've been running the tests on my impl (https://github.com/jmchacon/rusty6502) and everything on the base 6502 and NES variant I have in 100% agreement and that also lines up with my...

Consider this test case. A4 is odd, so there's an address error. Yet, the "final" value is incremented by 2, as if the post increment happened before or in parallel...