Silicon Photonic Device Design Competition

[lukasc-ubc]

$3,000 Elenion Silicon Photonic Device Design Competition

SiEPIC is hosting a design competition sponsored by Elenion Technologies with a $3,000 cash prize for the winner. The objective is to design and experimentally demonstrate a novel component, given a set of specifications and an optimization goal. The competition is open to anyone.

The component must be designed and modelled between February 6, 2018 and March 5, 2018, and submitted to us for fabrication by March 5, 2018 (Submission #1). We will fabricate your design via Applied Nanotools and/or the University of Washington, measure your devices (Maple Leaf Photonics), and provide you experimental data in late March. You will analyze the experimental data, and submit your design into the competition by the final deadline, 2 weeks after all the experimental data is provided (estimated deadline April 10, 2018) (Submission #2). The competition will be judged based on this experimental data.

Design objective:

• Broadband (1460-1640 nm), Dual-Polarization (TE, TM), 50/50 splitter.

Specifications:

• Port 1, input: 450 nm strip waveguide

• Port 2 and 3, two outputs: 450 nm strip waveguides separated by 2.0 µm

• Broadband operation between 1460-1640 nm

• Dual-polarization: quasi-TE and quasi-TM, for both input and output

• Device can operate as a splitter or as a combiner

• The device maximum size is 50 µm in length, and 7 µm in height.

• We are setting the minimum feature size to be 60 nm, which is roughly compatible with the capabilities of non-phase-corrected immersion lithography [1]. The devices will be fabricated using electron beam direct writing.

Optimization goal:

• Minimize the excess insertion loss, IL = - 10 log10(0.5) + 10 log10 (Port 3 / Port 1) for both polarizations across the wavelength range

• Minimize the imbalance in the splitting ratio, SR = abs(10 log10 (Port 3 / Port 2)), for injection in Port 1, for both polarizations across the wavelength range

• Figure of Merit (FOM) = max(IL-Experimental) + max(SR-Experimental), where max is the worst-case value across the measurement wavelength range and the worst-case for the two polarizations.

• The wavelength range for the analysis is defined as a wavelength span of 50 nm centred at the grating couplers’ peak response. Spectral smoothing with a uniform window of 1 nm is permitted.

Online silicon photonics course:

• This competition is being run in conjunction with the edX Silicon Photonics Design, Fabrication and Data Analysis course. This course includes commercial design and modelling tools which you may use for the competition. The course is optional for the design competition.

Fabrication and test details, Submission # 1 – deadline March 5, 2018, 9:00 pm Pacific Time:

• Fabrication is a single etch with a 220 nm silicon on insulator wafer. Fabrication process details are here: NanoSOI.

• Create three layouts for fabrication, using the templates provided in the SiEPIC-EBeam-PDK on GitHub (in the folder: klayout_dot_config/tech/EBeam/pymacros/SiEPIC-EBeam-competition):

  • 1. Cut-back method for insertion loss (IL), TE, with N = [0, 56, 112] splitters. Filename: openEBL_competition2018T1_TE_<your_GitHub_username>.gds
  • 2. Cut-back method for insertion loss (IL), TM, with N = [0, 56, 112] splitters. Filename: openEBL_competition2018T1_TM_<your_GitHub_username>.gds
  • 3. MZI extinction ratio test structure to extract splitting ratio (IR), for TE and TM. Filename: openEBL_competition2018T1_MZI_<your_GitHub_username>.gds

• Each layout should contain your device. Please replace <your_GitHub_username> with your username in all locations (filename, top cell names, opt_in labels)

• Verify your layout using the open-source verification tool provided in the EBeam PDK.

• Upload the layout following the instructions here: https://www.linkedin.com/pulse/openebl-fabrication-test-passive-silicon-photonic-lukas-chrostowski/.

• Verify that your layout was successfully received, merged, and that there are no errors.

• Please note that we are merging all submissions onto a single chip which we will keep for testing. Those interested in obtaining their own chip(s) can purchase than directly from one of the providers listed above.

Design competition, Submission # 2 – deadline April 10, 2018, 9:00 pm Pacific Time:

• A report describing your design. You may pursue a publication of work, in which case a draft version of your manuscript can be submitted as your report.

• Simulation results including a corner analysis to consider fabrication variations with process corners defined as ∆w = +/- 10 nm, and ∆h = +/- 10 nm, simulated over a wavelength range of 1460 - 1640 nm, for both TE and TM polarizations.

• Simulation files

• Experimental data analysis, including a calculation of the FOM defined above.

• Optional: A compact model, which calculates the device response for any input to any output combination (e.g., input on Port 2, output on Port 1), for one or both polarizations (e.g,. Injection of both TE and TM light in Port 1)

• Optional: A compact model that is suitable for Monte Carlo simulations, namely the compact model should be parameterized (e.g., interpolation) within the process corners

• A PPT file of not more than 10 slides, summarizing your methodology, design, and results

• Submit your entry to the following Dropbox link: https://www.dropbox.com/request/fjsLwzObsaybbqRigsGx

• Optional: If you are interested in encouraging others to use your component, you may submit it to the SiEPIC-EBeam-PDK on GitHub as a pull request, with files placed in the following locations:

  • 1. the report and simulation files in the folder Documentation/2018T1_Design_Competition (create a subfolder for your username),
  • 2. GDS file of the component in the folder klayout_dot_config/tech/EBeam/pymacros/SiEPIC-EBeam-competition
  • 3. A compact model, ebeam_competition_splitter_<your edX username>.ice, in the folder Lumerical_EBeam_CML/EBeam,
  • 4. State the value obtained for the FOM in the pull request comment.

Prize:

• The prize is offered by Elenion, in order to promote interest in novel silicon photonic design

• The cash prize will be awarded to the entry which

  • 1. beats the performance of the ebeam_y_1550 component in the EBeam PDK, which was fabricated using electron beam lithography and measured to have an excess loss of 0.3 dB (TE) and 0.43 (TM) at 1550 nm.
    • This component is based on the publication which was designed for TE (only) and fabricated using DUV lithography: Yi Zhang, Shuyu Yang, Andy Eu-Jin Lim, Guo-Qiang Lo, Christophe Galland, Tom Baehr-Jones, and Michael Hochberg, "A compact and low loss Y-junction for submicron silicon waveguide", Optics Express Vol. 21, Issue 1, pp. 1310-1316 (2013)
  • 2. achieves the best FOM while meeting all requirements and specifications.

• The prize committee (Dr. Michael Hochberg, Professor Michal Lipson, and Professor Lukas Chrostowski) will evaluate submissions on both the detailed results and on the methodology of the data analysis, at the discretion of the prize committee. In the event of a tie or other unexpected outcome, the prize committee may choose to split the prize at their discretion. All committee decisions are final.

• In case of problems, the metrics may be changed or updated, in which case the changes and an explanation will be posted publicly for all participants.

For questions, discussions, and updates, please see:

• https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK/issues/171

• Click on "Notifications" to receive email updates, including an announcement when the measurement results are available.

Legal

Participant agrees and acknowledges that by submitting a response, participating in the design competition and/or receiving any prizes or consideration in connection therewith: (i) he or she has the legal authority to enter into this competition and/or make submissions, and by entering into this competition and/or making a submission he or she is not violating any third party rights or obligations; (ii) each of SiEPIC and Elenion will have the right to use, reference and display the submissions, including participant’s name and likeness: (A) by publication on internal and public websites; (B) by publication in any and all media now or hereafter known, including without limitation, videotapes, audio recordings, photographs, print publications; (C) in printed and videotaped copies distributed to employees and present and potential customers; (D) in printed and videotaped copies distributed at sponsored or co­sponsored events; (iii) the winner shall be determined at the sole discretion of SiEPIC and/or the relevant judging committee; (iv) participant releases, discharges and waives any claims it may have against SiEPIC, Elenion or any of their affiliates, subsidiaries, owners, representatives, agents, employees, successors and beneficiaries whatsoever. Elenion shall not sponsor any prizes, financial or otherwise, that would cause it to violate applicable law.

References:

[1] See the following reference which illustrates imec’s fabrication silicon photonics capabilities with features down to 50 nm [1]. [1] S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, and G. Lepage, "193nm immersion lithography for high performance silicon photonic circuits," in Proc. SPIE, Mar. 2015, pp. 90520F-1.

Screenshots of the GDS layout templates:

[khavasi]

Hi The waveguide width in the provided layout templates is 500 nm but the width of waveguide in our design should be 450 nm according to the competition rules. How can we change the width of waveguides in the template? If it is not easy can we use a tapered waveguide to match the widths?

[lukasc-ubc]

@khavasi, Good point. Will change the template files to use 450 nm waveguides rather than 500 nm. For your device, you can assume the input/output pins will be 450 nm.

[lukasc-ubc]

@khavasi I fixed the pins to be 450 nm in the GDS files. a369b1f405d2d64765e72e405bed57dda47dbe23

[gbfarias]

Dear Lukas From the NanoSOI fabrication process website, it seems like the Oxide deposition (cladding) is optionnal in the process. Could you confim that there will be the oxide deposition in the process? Thanks! Giovanni

[GerardoCastanon]

Dear Lukas I was reading the specifications of the Y-junction design competition and i have a question about the separation of port 2 and 3. I wonder if the value of 2 micrometers is correct?, it is a must? In the reference paper they use 0.2 micrometers.

Cheers, Gerardo

[lukasc-ubc]

@gbfarias Giovanni,

The process we will be using includes oxide.

We will fabricate your design using two facilities: 1) University of Washington, and 2) Applied Nanotools.

Here is a description of each:

Applied Nanotools, Inc. NanoSOI process:

The photonic devices were fabricated using the NanoSOI MPW fabrication process by Applied Nanotools Inc. (http://www.appliednt.com/nanosoi; Edmonton, Canada) which is based on direct-write 100 keV electron beam lithography technology. Silicon-on-insulator wafers of 200 mm diameter, 220 nm device thickness and 2 µm buffer oxide thickness are used as the base material for the fabrication. The wafer was pre-diced into square substrates with dimensions of 25x25 mm, and lines were scribed into the substrate backsides to facilitate easy separation into smaller chips once fabrication was complete. After an initial wafer clean using piranha solution (3:1 H2SO4:H2O2) for 15 minutes and water/IPA rinse, hydrogen silsesquioxane (HSQ) resist was spin-coated onto the substrate and heated to evaporate the solvent. The photonic devices were patterned using a Raith EBPG 5000+ electron beam instrument using a raster step size of 5 nm. The exposure dosage of the design was corrected for proximity effects that result from the backscatter of electrons from exposure of nearby features. Shape writing order was optimized for efficient patterning and minimal beam drift. After the e-beam exposure and subsequent development with a tetramethylammonium sulfate (TMAH) solution, the devices were inspected optically for residues and/or defects. The chips were then mounted on a 4” handle wafer and underwent an anisotropic ICP-RIE etch process using chlorine after qualification of the etch rate. The resist was removed from the surface of the devices using a 10:1 buffer oxide wet etch, and the devices were inspected using a scanning electron microscope (SEM) to verify patterning and etch quality. A 2.2 µm oxide cladding was deposited using a plasma-enhanced chemical vapour deposition (PECVD) process based on tetraethyl orthosilicate (TEOS) at 300ºC. Reflectrometry measurements were performed throughout the process to verify the device layer, buffer oxide and cladding thicknesses before delivery.

Washington Nanofabrication Facility (WNF) silicon photonics process:

The devices were fabricated using 100 keV Electron Beam Lithography [1]. The fabrication used silicon-on-insulator wafer with 220 nm thick silicon on 3 μm thick silicon dioxide. The substrates were 25 mm squares diced from 150 mm wafers. After a solvent rinse and hot-plate dehydration bake, hydrogen silsesquioxane resist (HSQ, Dow-Corning XP-1541-006) was spin-coated at 4000 rpm, then hotplate baked at 80 °C for 4 minutes. Electron beam lithography was performed using a JEOL JBX-6300FS system operated at 100 keV energy, 8 nA beam current, and 500 µm exposure field size. The machine grid used for shape placement was 1 nm, while the beam stepping grid, the spacing between dwell points during the shape writing, was 6 nm. An exposure dose of 2800 µC/cm2 was used. The resist was developed by immersion in 25% tetramethylammonium hydroxide for 4 minutes, followed by a flowing deionized water rinse for 60 s, an isopropanol rinse for 10 s, and then blown dry with nitrogen. The silicon was removed from unexposed areas using inductively coupled plasma etching in an Oxford Plasmalab System 100, with a chlorine gas flow of 20 sccm, pressure of 12 mT, ICP power of 800 W, bias power of 40 W, and a platen temperature of 20 °C, resulting in a bias voltage of 185 V. During etching, chips were mounted on a 100 mm silicon carrier wafer using perfluoropolyether vacuum oil. Cladding oxide was deposited using plasma enhanced chemical vapor deposition (PECVD) in an Oxford Plasmalab System 100 with a silane (SiH4) flow of 13.0 sccm, nitrous oxide (N2O) flow of 1000.0 sccm, high-purity nitrogen (N2) flow of 500.0 sccm, pressure at 1400mT, high-frequency RF power of 120W, and a platen temperature of 350C. During deposition, chips rest directly on a silicon carrier wafer and are buffered by silicon pieces on all sides to aid uniformity.

[1] R. J. Bojko, J. Li, L. He, T. Baehr-Jones, M. Hochberg, and Y. Aida, "Electron beam lithography writing strategies for low loss, high confinement silicon optical waveguides," J. Vacuum Sci. Technol. B 29, 06F309 (2011)

[lukasc-ubc]

@GerardoCastanon, Dear Gerardo,

The requirement for having the output waveguides be separated by 2 µm is so that the splitter can be used in practical applications, namely where we have two independent waveguides that can be connected to other things. With the output waveguides spaced at 0.2 µm, the waveguides are actually strongly coupled (like a directional coupler), so one needs to separate them first before connecting to other waveguides. Part of the design challenge is engineering how you split the waveguides apart (and making it compact). Typically people use an S-Bend for that.

You can take a look at the SEM image of the Y-branch above for an example. Also the layout for that ybranch is included in this EBeam PDK.

Thanks for participating!

regards, Lukas

[vatalogg]

Dear Professor Lukas,

First, thank you for actively supporting us for the competition. I have got 2 questions, the first for the design and the second for the evaluation.

(A) It is mentioned that "the minimum feature size is 60 nm". How does that affect our design in terms of specific design rules? For example, does it imply something about the minimum distance between two silicon waveguides? Also, if, for any reason, I have a silicon trapezoid should the smallest (parallel) side have a length of at least 60 nm?

Lastly, are these design rules verified through the KLayout (similarly I have seen a DRC check in a VLSI design software) or it is just that our circuits will be distorted if we violate them?

(B) The insertion loss is negative through: IL = - 10 log10(0.5) + 10 log10 (Port 3 / Port 1), with the best value being zero (when Port 3/Port 1=0.5). So, I assume that we should minimize the value of abs(IL). Please correct me, if I misunderstood something.

Sincerely, Vasileios

[khavasi]

Hi Lukas, I encountered a problem in uploading my files. I used this link: http://upload.siepic.ubc.ca/openEBL.php and I received a message that the file has been successfully uploaded. But when I checked these links: http://upload.siepic.ubc.ca/openEBL/openEBL.txt http://upload.siepic.ubc.ca/openEBL/openEBL_coords.txt?lipi=urn%3Ali%3Apage%3Ad_flagship3_pulse_read%3BrjYJ8yqcSWWuEgfKBHbGSw%3D%3D I could not find details of my gds file. I tried several names for my gds file (and its top cell) and the last one was openEBL_khavasi_MZI.gds with top cell name openEBL_khavasi_MZI. Thank you in advance for your consideration.

[lukasc-ubc]

@vatalogg, Vasileios,

A) Min feature size of 60 nm, means that the minimum distance between any two pieces of silicon has to be 60 nm or more. A trapezoid (e.g., nanotaper) can have a tip that is at least 60 nm. Take a look at the file "ebeam_competition2018T1_example.gds" which shows the min feature for the tip being 60 nm.

The rules are there to help ensure that the facility can fabricate what you design. Foundries typically enforce these rules. Indeed there is a DRC check like in VLSI design. We have a DRC check file, which is the menu SiEPIC | Verification | DRC. It is presently in the master copy on GitHub, but not yet released through Package Manager.

B) Insertion Loss: Indeed, better minimize abs(IL) the way I (incorrectly) defined it.

[lukasc-ubc]

@khavasi

I just turned on the openEBL submission system. I turn it off on each fabrication run.

I see your openEBL*.gds files are there.

[khavasi]

Would you mind deleting my files? I'll upload them again later.

[lukasc-ubc]

Here is a video excerpt from an edX Phot1x Live Q&A, where I discussed how to simulate a component from a layout in KLayout, using Lumerical FDTD. The simulation generates the S-Parameters, which are loaded into INTERCONNECT, and which allows for Circuit Simulations.

https://youtu.be/qWtbPcVbAbY

[lukasc-ubc]

Dear Luhua

Based on what you read about waveguide separation, what I have drawn (2.5 center to center) should be sufficient.

In terms of the space, you don’t need a 100 nm waveguide intrusion. What is needed are pins on layer 1/10, but these are not fabricated (they are only used for identification). So you have the full length available.

Thanks for participating!

[LuhuaXu]

Hi Lukas, thanks for your reply! Please correct me if what I understand is wrong: The pins with length of 0.2 um on layer 1/10 are only for identification purpose, and they will not be fabricated; only structures on layer 1/0 will be fabricated.

[lukasc-ubc]

@LuhuaXu : Correct.

[LuhuaXu]

Hi Lukas, I am wondering if there is any restriction if I want to purse a journal publication for the device fabricated in this competition?

Thanks!

[LuhuaXu]

@lukasc-ubc Hi Lukas, I am also wondering if the SEM images could be provided for the fabricated device?

Thanks!

[vinhinpl-gist]

Dear Professor Lukas, Is it required that my design should be novel idea? In other words, can I utilize some idea from a published paper? Thank you, Vinh Nguyen

[lukasc-ubc]

@LuhuaXu,

Journal publication: of course!

SEM: yes, we can take a picture of your design. To request an SEM image, please place a box over the region of interest on layer 26.

[lukasc-ubc]

@vinhinpl-gist,

Nothing novel is required. You can use published designs and ideas if you wish.

[vinhinpl-gist]

@lukasc-ubc,

Thank you for your information.

[lukasc-ubc]

All,

I was pointed out to me that the template files I provided had an inconsistent filename compared to the instructions above. I have updated this, as openEBL_competition2018T1_TE_<your_GitHub_username>.gds

In commit 281df17def1d1b380f3118ff7e253c935353b392

[LuhuaXu]

@lukasc-ubc Thanks! I am wondering if I can take multiple SEM images (around 4)?

[lukasc-ubc]

@LuhuaXu,

Each image costs us about $25. So unless there is a good reason to take more pictures, I'd like to provide 1 image. If you would like to pay for more, we can arrange that.

[vinhinpl-gist]

@lukasc-ubc Can I submit 2 different designs if they are both satisfied the competition requirements?

[lukasc-ubc]

@vinhinpl-gist,

Multiple different designs: yes.

[vinhinpl-gist]

@lukasc-ubc

Yes. Thank you a lot.

[LuhuaXu]

@lukasc-ubc Thanks a lot!

[lukasc-ubc]

@vinhinpl-gist, @LuhuaXu, @khavasi, @vatalogg, @gbfarias, and others,

A reminder about the deadline for submitting to the competition: March 5, 2018, 9:00 pm Pacific Time

Please check the openEBL.gds file to make sure your design files are in there: http://upload.siepic.ubc.ca/openEBL/openEBL.gds

I look forward to seeing your submission!

regards Lukas