Digital-Logic-Sim
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visual bug: able to make chips overlap
first i have my chips:
then i customize aaaaaaaaaa to have taller size:
and they are overlapping, but usually if itried dragging something onto something it doesnt work, but it works here because i never dragged, dont know how you would prevent this though
In comparison, Turing Complete detects components changing size and automatically removes them from your circuit, which isn't always the behaviour one wants either.
I think this should stay as-is, to avoid breaking projects, it is only a visual bug after all