Digital-Logic-Sim
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SebLague
Buffer-like Delay using isCyclic not persisting into saved component
This was a bit of a hack in order to get a Buffer-like component, but I essentially took an AND gate, wired both A and B inputs into single SIGNAL IN. I then went into the text file and enabled "isCyclic" intentionally. The end result is a Buffer where the output will power on one "tick" after the input is powered on. This works great for a clock assembly, like so:
However, when I use this to create a component, the logic for the delay is gone and the clock never oscillates. I can provide my save file if need be.
the "Buffer" component, illustrating the forced "isCyclic" flag
{ "name": "BUF", "creationIndex": 6, "colour": { "r": 0.7641509771347046, "g": 0.40998053550720217, "b": 0.19103774428367616, "a": 1.0 }, "nameColour": { "r": 1.0, "g": 1.0, "b": 1.0, "a": 1.0 }, "componentNameList": [ "SIGNAL IN", "SIGNAL OUT", "AND" ], "savedComponentChips": [ { "chipName": "SIGNAL IN", "posX": -7.6431, "posY": 0.67, "inputPins": [], "outputPinNames": [ "IN" ] }, { "chipName": "SIGNAL OUT", "posX": 7.6431, "posY": 0.757, "inputPins": [ { "name": "OUT", "parentChipIndex": 2, "parentChipOutputIndex": 0, "isCylic": true } ], "outputPinNames": [] }, { "chipName": "AND", "posX": -2.5327, "posY": 0.6177, "inputPins": [ { "name": "A", "parentChipIndex": 0, "parentChipOutputIndex": 0, "isCylic": false }, { "name": "B", "parentChipIndex": 0, "parentChipOutputIndex": 0, "isCylic": true } ], "outputPinNames": [ "OUT" ] } ] }
An interesting side-effect of this BUF object.
This output will be delayed by 4 "ticks" from the input.
A similar, simpler case: a NOT connected to itself and the output functions as a clock, but when used as a component it doesn't output anything.
I think I figured out why. the "flow" of a powering on propagates each tick, but the cutting of power is immediate. in other words your clock has the power pulled before it's power can reach anything.
cutting the clock speed in half seems to work better as a clock because of the delayed-on but instant-off issue.
Even more fun with this little hacked component: a rising and falling edge detector: RISING goes high for one tick when IN goes high FALLING stays high except for one tick when IN goes low
"BUF" component will delay a HIGH signal by one tick, but will go low instantly "CAP" component will delay a LOW signal by one tick but will go high instantly - this is made with a NOT -> BUF -> NOT as which is what's in the FALLING leg.