SebLague
delay chip
Circuits in DLS have no concept of time - delaying "1 second" has no meaning - particularly since the speed of the simulation can be changed. if you want to delay something going High or Low a given number of clock cycles, use a Counter circuit.
This can be done on the latest release (Sorta).
One problem with this method is that it can only handle one cycle at a time, so multiple fast inputs will not output the same number fast outputs after a delay, but rather one output after a delay.
Notes for the following photo: Delay is in steps, 1+999 = 1000 steps. I'm at a target steps per second of 1000, so this will delay by about 1 second. Buses are simply used to circle and provide descriptions for blocks of chips.
I designed a delay for my clock generator. This delay design has a stable output instead of 1 tick pulsing. It also requires only one Pulse chip and less NAND gates.
It delays turning on, while instantly turning off. (I'm sure if needed, it can be refined that it both delays turning on and turning off)
Design:
