Digital-Logic-Sim

Digital-Logic-Sim copied to clipboard

App unusable because of very small window

3

Whenever I open this It opens it in a very small window which makes it unusable:  It doesn't even let me maximize it.

Anay-v2

How to make an OR gate?

2

I have tried to make an OR gate, but because there isn't a way to connect 2 wires to 1 output, I can't do it. How do I make one??

MiniMinnoww

How do I remove projects that I dont want?

Hjalram

All forks and PRs merge

42

This is a quick merge of all pull requests and forks. ## Download new Community Edition versions at [Digital-Logic-Sim-CE/releases](https://github.com/DigitalLogicSimCommunity/Digital-Logic-Sim-CE/releases/latest). (Current: v0.38) PD. Import and export chips does not work on...

AOx0

SSSDNSY

linux

17

How do i run this on linux.

zachariahstauffer

Circuit fails if compiled

3

The clock is a NOT gate, connected to the pause pin and self wired xor, that self wired xor is connected to an and gate, which is connected to EN...

radiantgurl

Ascii display

2

Ascii display using the 8 bit bus wire

carson-coder

Not saving when it should be?

14

Hi there. Throughout today I have been playing around with DLS. I had stopped to get something for lunch, so I had closed the app. I have now come back...

Owen7000

Add 4, 8, and 16 bit bus wires

4

This PR implements idea from #13.

t4ccer