STMicroelectronics
D1 Domain Core prescaler array "D1CorePrescTable[16]" non-zero values for values from 0b0100 to 0b111
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Describe the set-up
- STM32H755ZIQ
- uVision V5.39.0.0
Describe the bug in the system_stm32h7xx_dualcore_boot_cm4_cm7.c file, the function SystemCoreClockUpdate divides the value in the variable common_system_clock based on the four D1CPRE bits of the RCC_D1CFGR register. If the bits are 0b0000 to 0b0111 (0 to 7), sys_clk is not divided, but the first 8 value of the array D1CorePrescTable[16] are {0, 0, 0, 0, 1, 2, 3, 4}, which might cause a problem.
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
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