QSPI FIFO Threshold mask wrong

[jealcuna]

Describe the set-up

• stm32h750 mcu

Describe the bug The bug is located in stm32h750xx.h on 1.10.0 fw package

#define QUADSPI_CR_FTHRES_Pos (8U) #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */

Reference manual in QUADSPI chapter page 900 indicate FTHRES can take values from 0 to 31 in 5bits sub register size. However stm32h750xx.h has a mask for 4bits sub register size.

How To Reproduce

1. Download stm32cube h7 fw packager 1.10.0

2. Use QSPI peripheral with fifo threshold 32 bytes and generate the code with cube ide or cube mx

3. Check CR register looking for FTHRES and you will realize that value is 15 (0xf) equivalent a threshold for 16 bytes

[ASELSTM]

ST Internal Reference: 129927

[ASELSTM]

Hi @jealcuna,

Thank you for your contribution. This issue has been fixed in the frame of version v1.11.0 of the STM32CubeH7. Please allow me then to close this thread.

With regards,