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Published 20 hours ago • verified publisher icon SI-RISCV

Testbench error

Open xiaoliyang1 opened this issue 5 years ago • 2 comments

hello!Because I want to observe the waveform of e203, I use vcs and verdi, but there is no waveform in the output. The problem is as follows:

Fatal: "/home/xly/xly/11.19/e200_opensource/vsim/run/../install/rtl/general/sirv_gnrl_xchecker.v", 41: tb_top.u_e203_soc_top.u_e203_subsys_top.u_e203_subsys_main.u_e203_cpu_top.u_e203_cpu.u_e203_itcm_ctrl.u_sram_icb_ctrl.u_byp_icb_cmd_buf.u_bypbuf_fifo.dp_gt0.wptr_vec_0_dfflrs.sirv_gnrl_xchecker.CHECK_THE_X_VALUE: at time 17594

Error: Oops, detected a X value!!! This should never happen.

$finish called from file "/home/xly/xly/11.19/e200_opensource/vsim/run/../install/rtl/general/sirv_gnrl_xchecker.v", line 41. $finish at simulation time 17594

xiaoliyang1 avatar Nov 26 '19 08:11 xiaoliyang1

I have the same problem in modelsim！！！

Toxic-Scofield avatar Jun 19 '20 07:06 Toxic-Scofield

Hello，have you solved it？

Toxic-Scofield avatar Jun 19 '20 12:06 Toxic-Scofield