Rot127
Rot127
> I just had to disable the ARM code as that code made compilation fail with Visual Studio. VS reports errors in 2 of the ARM files for me. Please...
I am so grateful you guys use AArch64 so early and are so thoroughly checking it. I cannot thank you enough! SVE and SME2 added so much more complexity, this...
> I've been eagerly awaiting the LLVM 18 aarch64 Just to ensure we are on the same page. AArch64 on the `next` branch is already based on LLVM-18. ARM not...
> Opcode AArch64_MRS (0x42d03bd5) currently has the NZCV register as an implicit write register. This isn't correct LLVM doesn't distinguish apparently between MSR instruction which set it and which not:...
Some more comments regarding the flawed access information: > `casal` The memory operand should be `RW`. The access property is in respect to the memory operand, not for the single...
> We are happy to log these errors so that the project in the long run can be made better. Especially for AArch64 I would be super grateful if you...
Please open a new issue if you find more. So this one gets not too long. Can be again a collection issue.
> I would fix (partly) the casal instruction before the Alpha release. But the others take too much time. > eor and others require new code and fcvtn2 is so...
Closed in favor of: https://github.com/capstone-engine/capstone/issues/2588 https://github.com/capstone-engine/capstone/issues/2589
Is this a fix? If yes, please open a PR with it and add a test case.