VHDL-Mode does not support grammar for statements: protected and protected body

[timothystotts]

VHDL-2002 and VHDL-2008 defined a thread-safe, object-oriented type called "protected" type. Please refer to the VHDL LRM.

An example source that has protected-type issues with Sublime Text, but compiles for test-bench just fine. The protected type can be defined in a package + package body, or in an architecture preamble. It provides a way to define a thread-safe type to aggregates data, procedure, and impure function into a single type definition. It is perhaps the most crucial data type for an advanced test-bench. (My opinion.)

Quoting from:

https://github.com/timothystotts/fpga-serial-acl-tester-1/blob/main/ACL-Tester-Design-Single-Clock-VHDL/Testbench/pmod_acl2.vhdl

In the package:

	-- A protected complex type to implement a 8-bit logic vector register
	-- with access to shared between multiple architecture processes. 
	type t_share_reg is protected
		impure function Get return std_logic_vector;
		procedure Set(constant c_reg    : in std_logic_vector(7 downto 0));
		procedure Update(constant c_bit :    std_logic; constant c_pos : natural range 0 to 7);
	end protected t_share_reg;

In the package body:

	type t_share_reg is protected body
		variable v_reg : std_logic_vector(7 downto 0) := (others => '0');

		impure function Get return std_logic_vector is
		begin
			return v_reg;
		end function Get;

		procedure Set(constant c_reg : in std_logic_vector(7 downto 0)) is
		begin
			v_reg := c_reg;
		end procedure Set;

		procedure Update(constant c_bit : std_logic; constant c_pos : natural range 0 to 7) is
		egin
			v_reg(c_pos) := c_bit;
		end procedure Update;
	end protected body t_share_reg;

I'd like to request if you could fix the syntax highlighting, as the indentation beautification, to support protected types.

[Remillard]

I'll see what I can do. Typing is a very hard one to correctly scope because there are so many different variations that are possible. Sublime doesn't just do keyword highlighting, it's fully lexically scoped. Thus the syntax file is commensurately large and complicated.

However I don't disagree that it's important, but it's not a trivial task and my time is greatly reduced from when I first made the package (My VHDL-2019 variation where I tried to really restructure everything from a grammatical ground point is more or less permanently on hold). I'll see what I can do.