VHDL-Mode
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Parenthesis in `case` expression not scoped as punctuation
The parenthesis in an if conditional is scoped as follows (for example):
vhdl-mode: source.vhdl meta.block.architecture.body.vhdl meta.block.process.body.vhdl meta.block.if.conditional.vhdl meta.group.parens.vhdl punctuation.group.parens.begin.vhdl
The parenthesis in a case expression is scoped as follows (for example):
vhdl-mode: source.vhdl meta.block.architecture.body.vhdl meta.block.process.body.vhdl meta.block.if.body.vhdl meta.block.case.expression.vhdl
Seems like case expression should also have the punctuation scope at the end.