risc-v support

[richardeoin]

Example is still WIP

[hegza]

I used this branch to successfully write an application for a virtual prototype of a riscv32imac (VexRisv), though I had to remove #include "tensorflow/lite/schema/schema_generated.h" from micro_interpreter.rs to make it work on my machine. I'm going to guess it's a problem on my end.

The first commit provides direct value for anyone targeting RISC-V and is non-intrusive to build otherwise, therefore I'd upvote merging that.

Have to appreciate the fact that a single commit addresses two compiler bugs 😃