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hipcc does not hipify __nvvm_get_smem_pointer function

3

In many CUDA related project, we can see the line of code as the following: ``` extern "C" __device__ uint32_t __nvvm_get_smem_pointer(void *ptr); ``` It is used to convert the shared...

terU3760

Inline assembly of DS_WRITE_B128 compile error Don't know how to handle indirect register inputs yet for constraint 'v'

1

By referencing [here](https://github.com/adityaatluri/gemm-vega64/blob/master/shared_ops.h), wrote the following inline assembly code: ``` inline __device__ void sts(uint32_t ptr, uint4 val) { asm volatile("DS_WRITE_B128 %0, %1;\n" : : "v"(ptr) , "v"(val)); } ``` But...

terU3760

How to convert LDS memory address to the address can be passed into DS_READ_* and DS_WRITE_* instructions?

2

Have followed [here](https://github.com/RadeonOpenCompute/hcc/issues/693) to write the following code: The hip file: ``` #include "hip/hip_runtime.h" #include "hip/hcc_detail/device_library_decls.h" __global__ void halfVec_v_pk_sts_then_lds( uint16_t * dst , uint32_t * ptr , uint16_t * val...

terU3760

@rocm-hcc We are going to enforce two factor authentication in (https://github.com/RadeonOpenCompute/) organization on 7th April , 2022 . Since we identified you as outside collaborator for this organization, you need...

DeeptimayeeSethi

Hi I cant run chai benchmark in gem5gcn3, would you please if you have any informations about running benchmarks in gem5gcn3(also gem5gpu) tell me. Thanks regard

twilight1996

Need support for AMD Ryzen Embedded V1000/APU

7

Currently, AMD Ryzen Embedded V1000 and APU are not supported by HCC which does not allow Tensorflow to take advantage of the APU power coming from AMD Ryzen Embedded V1000...

jarvis-hal

extractkernel for rdc code

2

Hi all, I tried to write a __global__ kernel and a __device__ function and compile __device__ function in a relocatable way(-fgpu-rdc). Then I tried to use extractkernel script to dump...

brad-mengchi

What constraints can be used in operand list in inline assembler for amd gcn?

2

For some amd gcn instructions can be used "high" level llvm features like this (some are already defined in such way in hc.hpp like __amdgcn_ds_bpermute): ``` c++ ulong __amdgcn_mqsad_pk_u16_u8(ulong, uint,...

misos1

It seems as all of the @ghostplant links are now 404. Is there a guide or set of steps called out somewhere for supporting the GFX902? This is the graphics...

taichichuan

HCC build HIP from source at ARM64 Ubuntu 16.04 error out

5

export HIP_PLATFORM=hcc cmake -DHSA_PATH=/opt/hsa-rocr-dev/hsa -DHCC_HOME=/opt/rocm/hcc -DCMAKE_INSTALL_PREFIX=/opt/rocm/hip -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_FLAGS= "-v" .. #make fatal error: error in backend: Unsupported calling convention. clang-7: error: clang frontend command failed with exit code 70 (use...

wormwang