pycachesim

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cachesim: backend.c: added support for 4 bit LFSR (pseudo random) replacement algorithm, added fuction to get all dirty lines in a given level as a list cachesim: cache.py: changed few...

mahendraVamshi

Segfaults with 64bit addresses

1

I see that 64bit support was added pretty recently. I get a lot of nondeterministic segfaults when trying to use the backend.c by itself. Randomly on these line: https://github.com/RRZE-HPC/pycachesim/blob/1741d353473206f4322760335ba43855673ed43a/cachesim/backend.c#L187 https://github.com/RRZE-HPC/pycachesim/blob/1741d353473206f4322760335ba43855673ed43a/cachesim/backend.c#L154...

MintPaw

Currently a Write Allocate Miss leads to a LOAD on the same cache level. This in-turn produces a LOAD and MISS in the statics. A better solution would be to...

cod3monk

Online VTK Visualization

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Online/live visualization support using vtkInterface. To install use `pycachesim[ONLINE_VIS]`. - [ ] When visualizing `CacheSimulator` show all at the same time (e.g., in multiple or different colors) - [ ]...

cod3monk