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cpu/esp32: add support for ESP32-S3
Contribution description
This PR is a split-off from PR #18185, which provides
- the support for ESP32-S3 SoC
- a common ESP32-S3 board definition
- the board definition for the ESP32S3-DevKit board.
This PR requires PRs ~#18408, #18409, #18410 and #18411~ to be compilable in CI. Furthermore the CI workers need an update with riotdocker #200
Testing procedure
Beside of Green CI some basic tests should work (Of course, I have already tested all of them and many more):
-
tests/shell
-
tests/periph_cpuid
-
tests/periph_gpio
-
tests/periph_hwrng
-
tests/periph_i2c
-
tests/periph_spi
-
tests/periph_rtt
-
tests/periph_timer
-
examples/gnrc_networking
usingesp_wifi
as optional module.
Issues/PRs references
~Depends on #18408 Depends on #18409 Depends on #18410 Depends on #18411~
@kaspar030 This PR requires an update of CI workers. Is there a plan when it is done next time? How is it coordinated?
@benpicco Do you think the CI workers are updated now?
Well it's worth a try. And with the current CI run times the compilation will happen during the night anyway.
If not we got something to point to showing that the automatic updates apparently do not work.
Well it's worth a try. And with the current CI run times the compilation will happen during the night anyway.
If not we got something to point to showing that the automatic updates apparently do not work.
The toolchain is still missing :worried:
Well it's worth a try. And with the current CI run times the compilation will happen during the night anyway. If not we got something to point to showing that the automatic updates apparently do not work.
The toolchain is still missing worried
The question is how we can get the CI worker up to date.
I'd keep the ready for build label set - makes it easier to complain about it on Matrix 😄
bumping for hopefully improved CI PR.
CI is not happy anymore
undefined reference to `cpu_coreclk'
CI is not happy anymore
undefined reference to `cpu_coreclk'
:worried: Hm, I compiled some tests before pushing the changes. That is, we need an extra CI compilation cycle, quite annoying.
CI is not happy anymore
undefined reference to `cpu_coreclk'
worried Hm, I compiled some tests before pushing the changes. That is, we need an extra CI compilation cycle, quite annoying.
I have moved CLOCK_CORECLOCK
definition to periph_cpu.h
, see commit e7bf789dd42cbbb4b4858799bcbed8824b0d98c2. Let's hope that it doesn't cause other compilation problems.
@benpicco I am getting desperate as I am getting another unrelated error in the CI compilation. I was hoping to merge the PR today to be able to provide the PRs based on it for the ESP32-S3 before my vacation starting tomorrow :worried:
The current CI run will fail due to unrelated issues. Failures that look like
-- running on worker breeze thread 3, build number 316686.
make: Entering directory '/tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/tests/driver_sam0_eth'
make: Leaving directory '/tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/tests/driver_sam0_eth'
make: Entering directory '/tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/tests/driver_sam0_eth'
Building application "tests_driver_sam0_eth" for "same54-xpro" with MCU "samd5x".
sha1sum /tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/build/tests_driver_sam0_eth.bin > /tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/build/test-input-hash.sha1
text data bss dec hex filename
19468 180 16932 36580 8ee4 /tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/build/tests_driver_sam0_eth.elf
make: Leaving directory '/tmp/dwq.0.3566048456678582/1bc9f0dc6a1abbb862a0fb9058807d10/tests/driver_sam0_eth'
32d31
< netdev_legacy_api
{"build/": 112}
will be fixed by https://github.com/RIOT-OS/RIOT/pull/18466
If it is passing mudock and acked there is no reason it can't be merged today or even after your vacation. Maybe we want to enable automerge?
Sorry this didn’t make it, enjoy your vacation! Let’s hope we’re getting CI fixed by the time you’re back 😄
I will build once we fix the CI
Thanks for reviewing and merging.