add controlflow handling to stochastic swap pass

[ewinston]

Summary

Adds controlflow handling to StochasticSwap routing pass.

Details and comments

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[coveralls]

Pull Request Test Coverage Report for Build 3200296423

• 181 of 195 (92.82%) changed or added relevant lines in 5 files are covered.
• 16 unchanged lines in 3 files lost coverage.
• Overall coverage increased (+0.03%) to 84.684%

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Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
qiskit/transpiler/passes/utils/check_map.py	18	19	94.74%
qiskit/transpiler/passes/routing/stochastic_swap.py	125	129	96.9%
qiskit/transpiler/passes/routing/utils.py	19	23	82.61%
qiskit/dagcircuit/dagcircuit.py	18	23	78.26%
<!--	Total:	181	195

Files with Coverage Reduction	New Missed Lines	%
src/optimize_1q_gates.rs	1	95.16%
src/results/marginalization.rs	1	72.99%
src/sampled_exp_val.rs	14	63.93%
<!--	Total:	16

Totals
Change from base Build 3199713912:	0.03%
Covered Lines:	61798
Relevant Lines:	72975

---

💛 - Coveralls

[ewinston]

A couple of issues I noticed while allowing control flow instructions to be less than full width:

1. the usage of for node in dag.two_qubit_gates may return CF instructions since these should get through the unrolling which could cause exceptions
2. sometimes it seemed possible for a CF instruction's num_clbits to get out of sync with the DAGOpNode.cargs using public methods. I can't remember how it occurred but if I do I'll create an issue.

[jakelishman]

For 1: when this method has been used in other transpiler passes, I've put in an explicit if isinstance(node.op, ControlFlowOp): continue at the start of the loop to avoid issues.

For 2: that seems a bit worrying. At a guess, perhaps it's if a clbit that's in the condition of the argument is also in the body of the blocks becomes idle in the blocks? For IfElseOp, the two blocks also need to have the wires be idle in both blocks to be removed again, which seems like a vector for issues.

[ewinston]

For 1: when this method has been used in other transpiler passes, I've put in an explicit if isinstance(node.op, ControlFlowOp): continue at the start of the loop to avoid issues. We could also set a flag on the DAGCircuit method which by default doesn't include two qubit CF instructions.

For 2: that seems a bit worrying. At a guess, perhaps it's if a clbit that's in the condition of the argument is also in the body of the blocks becomes idle in the blocks? For IfElseOp, the two blocks also need to have the wires be idle in both blocks to be removed again, which seems like a vector for issues.

That's a possibility. I usually didn't intend to remove idle classical bits but it's possible they slipped through somehere.

The pass only considers wires as idle as the intersection of idle wires of each block.

[jakelishman]

(Also, it perhaps wouldn't be a bad idea to rebase this PR to get rid of the accidentally re-applied commits from main - it's not really the end of the world, but if we merge as-is, about 11 people will falsely get claimed as co-authors.)