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Qiskit
CSP ignores 3-or-more-qubit gates
Information
- Qiskit Terra version: main
What is the current behavior?
Take the following circuit:
from qiskit import QuantumCircuit
qc = QuantumCircuit(3)
qc.cx(0,1)
qc.ccx(2,0,1)
qc.draw()
q_0: ──■────■──
┌─┴─┐┌─┴─┐
q_1: ┤ X ├┤ X ├
└───┘└─┬─┘
q_2: ───────■──
CSPLayout should not be able to find a solution with a layout 0- > 1 -> 2. However:
from qiskit.transpiler import CouplingMap
from qiskit.transpiler.passes import CSPLayout
pass_ = CSPLayout(CouplingMap([(0, 1), (1, 2)]))
result = pass_(qc)
pass_.property_set["CSPLayout_stop_reason"]
'solution found'
Suggested solutions
There are two options. If CSPLayout encounters a 3-or-more-qubit gate, either assumes that this needs complete connection among the involved qubits, or just fails with reason 3-or-more-qubit gate found.
@1ucian0 I tried to add 3-or-more-qubit gates as constraints, and the pass generates this layout:
Layout({
1: Qubit(QuantumRegister(3, 'qr'), 0),
0: Qubit(QuantumRegister(3, 'qr'), 1),
2: Qubit(QuantumRegister(3, 'qr'), 2)
})
I guess maybe it is reasonable? It does not involve swaps. It simply suggests that mapping qr[0] to physical qubit 1. Such mapping is allowed, right? It is kind of the point of using CSP in this pass.
In the original example, CCX does not have a possible layout in the coupling map 0 - > 1 -> 2. No solution should be found or raise.
@1ucian0 Just created a PR (#7625). Not sure if I can/should add you as a reviewer. Anyway, my first draft is there =)
un-assigning so that this issue is open for others to have a go. If anyone would like to pick this work up make sure to take a look at #7625 and go from there 😄
sorry for the slow reply @lmpawan10, I'll assign to you 😄 As this is an old issue the first step would be to check that the bug still exists
Sorry that I got busier with other tasks. I am planning to work on this issue this month. You can give it to others if they are interested, or I will deal with it.