[DAGCircuit Oxidation] Refactor bit management in `CircuitData`

[kevinhartman]

Summary

This is part of the work we're doing to port DAGCircuit to Rust. It's work I've pulled out of a local branch where I'm doing that port, in an effort to reduce the size of that eventual PR.

The primary improvement that this brings is the introduction of BitData, which encapsulates keeping Python and native bit indices in sync. It provides methods like map_indices and map_bits which improve the ergonomics of translating between native and Python bits at PyO3 boundaries.

Details and comments

• Added zero-cost struct types for our native Qubit and Clbit representation.
• Added a new struct BitData which encapsulates maintaining a mapping between native Rust bit types and Python bit types. This significantly cleans up the code in CircuitData and makes it reusable for DAGCircuit.
• Made InternContext into a more generic IndexedInterner data structure, which implements the new Interner trait with slotted interning for any T which is Hash and Eq.
• Added Interner trait, for defining interner semantics for containers like IndexedInterner.

The one caveat to this PR is that we now no longer share interning between Qubit and Clbit indices, since this is more difficult from a typing perspective. If we want to share a single IndexedInterner for both Qubit and Clbit operand lists, this would be possible, but we should revisit it. For now I wanted to just focus on keeping things strongly typed so that our Rust code doesn't get overly messy at this early stage.

[qiskit-bot]

One or more of the the following people are requested to review this:

• @Eric-Arellano
• @Qiskit/terra-core
• @kevinhartman
• @mtreinish

[coveralls]

Pull Request Test Coverage Report for Build 9192883136

Warning: This coverage report may be inaccurate.

This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.

• For more information on this, see Tracking coverage changes with pull request builds.
• To avoid this issue with future PRs, see these Recommended CI Configurations.
• For a quick fix, rebase this PR at GitHub. Your next report should be accurate.

Details

• 237 of 264 (89.77%) changed or added relevant lines in 5 files are covered.
• 3 unchanged lines in 1 file lost coverage.
• Overall coverage increased (+0.006%) to 89.62%

---

Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
crates/circuit/src/circuit_data.rs	79	84	94.05%
crates/circuit/src/bit_data.rs	87	94	92.55%
crates/circuit/src/interner.rs	30	45	66.67%
<!--	Total:	237	264

Files with Coverage Reduction	New Missed Lines	%
crates/qasm2/src/lex.rs	3	93.64%
<!--	Total:	3

Totals
Change from base Build 9163549280:	0.006%
Covered Lines:	62362
Relevant Lines:	69585

---

💛 - Coveralls

[kevinhartman]

I'm rethinking a bit of this PR (specifically the stuff with packing and interning) so I'm going to put this into draft for now.

The BitData stuff is likely to stay, but I'm likely to reduce the traiting stuff around packing and interning a bit.

[qiskit-bot]

One or more of the following people are relevant to this code:

• @Eric-Arellano
• @Qiskit/terra-core
• @kevinhartman
• @mtreinish