Pyverilog
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PyHDI
Python-based Hardware Design Processing Toolkit for Verilog HDL
I had the same problem as issue #116 However, I was able to fix the problem by adding a new type of number with the provided structure. Already made a...
Hello, I noticed that unsized literal number constants with the base specified (`'d0`) are supported but if the base is not specified (`'d`) it raises a ParseError exception : ```...
when exculd: ast, directives = parse(file, preprocess_include="", preprocess_define="") Got the following error: File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py", line 2338, in parse ast = codeparser.parse() File "C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py", line 2315, in parse text = self.preprocess()...
Hello, the following file could not be parsed: https://github.com/KatCe/pyverilog_issue_125/blob/main/picorv32_sv2v_out.v Got the following error: ``` Pyverilog/pyverilog/vparser/parser.py", line 1589, in p_if_statement_woelse p[0].end_lineno = p[5].end_lineno AttributeError: 'ForStatement' object has no attribute 'end_lineno' ```...
Seems the parser can not support "generate case" statement. Did not find grammar in Parser and raise a ParseError when handling verilog contains "generate case" statements.
In the definition of the `VerilogGraphGenerator` class, one of the arguments of its `generate` method is `do_reorder`: https://github.com/PyHDI/Pyverilog/blob/81838bc463d17148ef6872af34eb27585ee349ba/pyverilog/dataflow/graphgen.py#L57 However, in the `example_graphgen.py` file, this argument is mistakenly referred to as...
This pull requests addresses issue #44 by adding support for automatic functions. I updated lexer and parser to parse automatic functions. I updated the ast Function object with a boolean...
I'm tring to use pyverilog to parse one large scale design, but the ast.show() can't display all module's AST. How can I get all module's AST ?
I have some Specify statements in my Verilog code. It seems that Pyverilog cannot parse such statements?
I'm not sure if Pyverilog is any longer being actively supported or upgraded? I have made quite a few modifications in order to parse my in-house standard digital library, and...
