SVA assert / assume/ cover property support

[dyadav7]

Please add support of assert/assume/cover property syntax:

$ cat a.sv 
  module test (input clk, inp1, inp2);
  wire[5:0] cnt;
  A1: assume property (@(posedge clk) inp1);
  P1: assert property (@(posedge clk) cnt == 5);
  C1: cover property (@(posedge clk) cnt == 5);
 endmodule

I just want the parser to not generate the exception on above lines (see error.txt). I just need the very basic parsing support for the above property lines (do not need to parse the property expression, ...).

error.txt a.sv.txt

[shtaxxx]

I'm not sure, but the modification of the parser will not be small.