accelerator-wall
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Throughput calculations?
Hello! I'm interested in using a similar approach for deep learning training hardware, and had two questions related to throughput calculations.
- How did you get 'effective transistors' (the number that can be actively powered at once) out of existing chip datasheets?
- What calculation did you use to get throughput (effective transistors * frequency) for 5 nm chips from the IRDS report? I am trying to use a similar approach for nodes further down the line but find the report very hard to parse.