dso-quad-logic
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PetteriAimonen
Logic analyzer for the DSO Quad
A possible extra mode for a logic analyser is to decode uart signals. This can be handy when monitoring TTL serial output.
Create a FPGA logic to capture the signal and to store it in a FIFO. Add software support to read from the FPGA like this.
The open logic sniffer format is very simple: https://github.com/jawi/ols/wiki/OLS-data-file-format The OLS client has nice signal decoders etc, therefore it would be useful to support this format directly. Currently one has...
Currently the code slows down when the screen is zoomed out. This is because it needs to go through all the stored events in order to draw them. To speed...
To implement more advanced features, we need a menu in order to be able to configure and use them. The menu drawing code by Alexander Rössler is a good start....
Separate the following parts away from main.cc (in order of importance): 1) Signal capture; easy to separate, really doesn't belong there. 2) System setup 3) Graphics setup & main app...