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OpenXiangShan
dcache_tag_case1: 1.调用clear_cop_csrs标签(将控制状态寄存器清零) 2.写任意数据(0x233)入cop_tag_data(0x5cd) 3.写特定数据入cop_level(0x5c7,1)、cop_way(0x5c8,0x1)、cop_index(0x5c9,0x1)，写数据COP_WRITE_TAG(6)入cop_op(0x5c5) 4.调用wait_until_cop_finish_or_timeout(li t1, 0x0；li t0, 0x100)标签，等待寄存器cop_finish的值由0变1 5.调用clear_cop_csrs标签(将控制状态寄存器清零) 6.写与步骤3相同的特定数据入cop_level(1)、cop_way(0x1)、cop_index(0x1)，写数据COP_READ_TAG(2)入cop_op 7.调用wait_until_cop_finish_or_timeout标签，等待寄存器cop_finish的值由0变1 8.读寄存器cop_tag_data，如果读值与步骤2所写的数据(0x233)不相等，就报错 您好：请问关于dcache/icache中0x5c5、0x5c7-0x5c9、0x5cd，这几个自定义读写寄存器你们emu是怎么设置的，我跑了你们的case，但是csrw对这几个寄存器写0x0失败；
arch: add support for spike finished: 1. add _putc() for spike todo: 1. add other system calls for spike
arch: add support for spike manual: 1. make ARCH=riscv64-spike 2. fix HAS_RVV to support v extension finished: 1. fix bug ```#include ``` in am/src/nemu/isa/riscv/cte64.c 3. add tohost link rules in...
amtest -> mp test 多核仿真结果不一致，修改__barrier代码实现后一致了，是为什么？ 这是修改之前的仿真结果：  这是修改后的代码（上面的是原来的，后面的是我写的）以及仿真结果（vcs和verilator完全一致）：  
This PR addresses several compilation issues encountered when building for the RV32 architecture. ## Issues ### Compilation Errors in `_map_fault` The current implementation of `_map_fault` results in compilation errors, as...
使用 riscv64-xs编译时报错relocation truncated to fit: R_RISCV_HI20，编译器重新安装了也没法解决，使用-mcmodel=medany 选项也无法解决
/home/ccb/Desktop/nexus-am/apps/coremark/build/riscv64-xs//./src/core_portme.o: in function start_time': /home/ccb/Desktop/nexus-am/apps/coremark/src/core_portme.c:49:(.text+0xe): relocation truncated to fit: R_RISCV_HI20 against symbol start_time_val' defined in .sbss section in /home/ccb/Desktop/nexus-am/apps/coremark/build/riscv64-xs//./src/core_portme.o /home/ccb/Desktop/nexus-am/apps/coremark/build/riscv64-xs//./src/core_state.o: in function core_init_state': /home/ccb/Desktop/nexus-am/apps/coremark/src/core_state.c:133:(.text+0x1a): relocation truncated to fit: R_RISCV_HI20 against...
Add test for https://github.com/OpenXiangShan/XiangShan/pull/4044 Example log: ``` The first instruction of core 0 has commited. Difftest enabled. Setup Hello, World @ 0! Test === [0] Inject metaArray === ECC inject...
