Regarding the clock frequency for simulation

[Liujiaqi-jlu]

Before start

• [x] I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• [x] I have read the XiangShan Documents. 我已经阅读过香山文档。
• [x] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• [x] I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• [x] I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Hello, I would like to ask about the clock frequency of the emu simulated using Verilator. I am using the Nanhu v2.2docker version, and I noticed that the relationship between the command to generate the waveform and the corresponding waveform is that 1ps corresponds to one clock cycle. The calculated clock frequency is 1THz, which is a bit too high. I would like to ask if there is any proportional scaling between the actual clock frequency and the generated command?

[Ma-YX]

The clock frequency (clock cycles/time) in waveform during simulation is not the same as real chip after tape out.

As for clock frequency of Nanhu v2 simulation, it's based on (aligned with DRAMSIM3) 2 GHz.

[cebarobot]

By the way, the time in waveform doesn't make any sense. If you want, you could follow the verilator docuemnt to solve it.