About L2C hardware prefetcher configuration

[eeeeewwz]

Hi, I'm working on running SPEC06 checkpoints on XS-GEM5, and I notice that the default L2 hardware prefetcher is WorkerPrefetcher in the script simple_gem5.sh: https://github.com/OpenXiangShan/GEM5/blob/e62ce212124b229ad1b4bf6e9bac47b80df4dbb6/util/warmup_scripts/simple_gem5.sh#L130 But XiangShan now uses a multi-prefetcher framework for L2 Cache (i.e., SMS + BOP), as RTL code and the comment says: https://github.com/OpenXiangShan/GEM5/blob/e62ce212124b229ad1b4bf6e9bac47b80df4dbb6/util/warmup_scripts/simple_gem5.sh#L115 But when I follow the simple_gem5.sh and only change the option --l2-hwp-type=MultiPrefetcher, I got following error:

[<m5.params.AddrRange object at 0x7fc1c6882530>]
['basic']
db_switches: []
Attach 1 decoders to thread with addr: <orphan System>.cpu.decoder
Create threads for test sys cpu (RiscvO3CPU)
Add dtb for L1D prefetcher
AttributeError: Class MultiPrefetcher has no parameter queue_size

At:
  build/RISCV/python/m5/SimObject.py(852): __setattr__
  /home/prj/OpenXiangShan/GEM5/configs/common/CacheConfig.py(204): config_cache
  /home/prj/OpenXiangShan/GEM5/configs/example/fs.py(290): build_test_system
  /home/prj/OpenXiangShan/GEM5/configs/example/fs.py(424): <module>
  build/RISCV/python/m5/main.py(434): main

Is there any information or additional configuration I've missed? What does WorkerPrefetcher mean?